FIG. 7 shows a typical active-matrix-type image display device in a prior art, and gives illustration as a block diagram showing an electric structure of a liquid crystal display device 1. The liquid crystal display device 1 schematically includes: a display section 2; a scanning signal line driving circuit gd; a data signal line driving circuit sd; and a control signal generating circuit ct1. In the display section 2, as described above, there is provided a pixel PIX in each area, sectored in matrix by a plurality of scanning signal lines g1, g2, . . . , gm (hereinafter shown by a reference sign g when they are collectively referred) and data signal lines s1, s2, . . . , sn (hereinafter shown by a reference sign s when they are collectively referred).
As shown in FIG. 8, each pixel PIX includes: an active element SW and a pixel capacitor Cp. When the scanning signal lines g are selectively scanned, the active elements SW lead image signals DAT of the data signal lines s to the pixel capacitor Cp, so as to hold the image signals DAT also in the non-scanning period, thereby maintaining the display state. The pixel capacitor Cp is constituted of a liquid crystal capacitor CL and an auxiliary capacitor Cs.
The data signal driving circuit sd is constituted of a shift resistor 3 and a sampling circuit 4. In the data signal driving circuit sd, the shift resistor 3 performs sampling with respect to the image signals DAT that have been inputted to an analog switch of the sampling circuit 4 in synchronism with timing signals such as (a) a clock signal CKS from the control signal generating circuit ct1, (b) an inversion signal CKSB corresponding to CKS, and (c) a data scanning start signal SPS, so as to write the thus sampled image signal DAT in the data signal lines s as required.
The scanning signal line driving circuit gd is constituted of a shift resistor 5, and selectively scans the scanning signal lines g sequentially in synchronism with the timing signals such as (a) a clock signal CKG from the control signal generating circuit ct1 and (b) a scanning start signal SPG, so as to control ON/OFF of the active elements SW disposed in the pixels PIX. When the active elements SW are ON, the image signals DAT in the data signal lines s are written in the pixels PIX so as to be held by the pixel capacitor Cp disposed in each pixel PIX as described above. The operation described above is repeatedly performed, so that it is possible to display images on the display section 2.
FIG. 9 is a waveform chart showing an example of a drive waveform of the foregoing writing operation. In this example, a horizontal-line-inversion-type driving method is employed. The image signal DAT is outputted from the control signal generating circuit ct1 and is inputted to the data signal line driving circuit sd, in synchronism with the clock signals CKS, CKSB, and the data scanning start signal SPS. In this example, image signals of positive polarity are written in the pixels of odd-numbered scanning signal lines (g1, g3, . . . ), and image signals of negative polarity are written in the pixels of even-numbered scanning lines (g2, g4, . . . ). Moreover, the liquid crystal display device 1 is driven by the opposed AC drive. Thus, each image signal DAT includes an offset potential that is equivalent to a potential of Vcom of the counter electrode.
The data signal line driving circuit sd is described below in detail. FIG. 10 is a block diagram illustrating an example of a structure of the data signal line driving circuit sd. In FIG. 10, the reference number FF indicates a flip-flop. The FFs are serially connected in multi-stages so as to form the shift register 3. In the sampling circuit 4, nonconjunctions of respective outputs between the FFs are worked out by means of NAND gates a1 to an, so as to generate sampling signals smp1 to smpn, so that invertors inv1 to invn and analog switches asw1 to aswn are operated in accordance with the thus obtained sampling signals smp1 to smpn. In this way, the sampling circuit 4 supplies the image signals DAT of both polarities respectively to the data signals s1 to sn.
FIG. 11 is a timing chart for further detailed explanation on operation of the liquid crystal display device 1 thus arranged. As described above, the FFs and the NAND gates a1 to an generate the sampling signals smp1 to smpn, which respectively correspond to the data signal lines s1, s2, . . . sn, in response to the clock signals CKS, SKSB and the data scanning start signal SPS. In accordance with the sampling signals smp1 to smpn, the analog switches asw1 to aswn for both the polarities supply sequentially to the data signals s1, s2, . . . sn, the image signals DAT for realizing the opposed AC drive. In FIG. 11, the potential Vcom of the counter electrode for realizing the opposed AC drive is indicated by a broken line.
Here, the operation of the liquid crystal display device 1 is further described, drawing an attention to an i-th data signal line si. To begin with, when the sampling signal smpi becomes high level at time t1, the analog switch aswi is turned ON, so as to start charging the data signal line si with a potential Vdatap of the image signal DAT of positive polarity. In an almost same timing, the scanning signal lines gj are turned ON, so as to start charging a pixel capacitor Cp of a pixel of row j and column i with the potential Vdatap of the image signal DAT. When the scanning signal line gj is turned OFF, the charging of the pixel capacitor Cp is terminated (ended). When the sampling signal smpi becomes low level, the analog switch aswi is turned OFF, so as to float the data signal line si (so as to put the data signal line si in a floating condition), thereby terminating the charging of the data signal line si.
When the data scanning start signal SPS is inputted at time t2, so as to start a next horizontal scanning period, the potential Vcom of the counter electrode is changed from the low level to the high level, due to the opposed AC drive. Here, the data signal line si is electrically floated. For this reason, the potential of the data signal line si is also changed following the change in the potential Vcom of the counter electrode, thereby being increased to a sum of the potential Vdatap of the image signal DAT of positive polarity and the potential Vcom of the counter electrode, because the capacitance of the data signal line si and that of the counter electrode are coupled (that is, due to coupling capacitance between the data signal line si and the counter electrode).
Similarly, at time t3, the potential Vdatan of the image signal DAT of negative polarity is supplied, so that the next horizontal scanning period is started at time t4, thereby changing the potential Vcom of the counter electrode from high level to low level. In accordance with the change in the potential Vcom, the potential of the data signal line si is decreased to a sum of the potential Vdatan, and the potential Vcom. Therefore, caused in the data signal line si are potential changes Vdatap+Vcom, and Vdatan−Vcom, based on GND of a power supply of the data signal line driving circuit sd.
Here, for example, if Vdatap=7V, Vdatan=2V, and Vcom has an amplitude of 5V, the potential of the data signal line si is 12V at time t2, and −3V at time t4. Thus, in this case, it is necessary to set the data signal line driving circuit sd to have a power supply potential VDD of 12V or more, and a power supply potential VSS of −3V or less. If the power supply potential VDD is lower, or the power supply potential VSS is higher, the data signal line si has a potential higher than that of the sampling signal smpi, which drives a gate of the analog switch aswi, the gate being connected to the data signal line si. This may influence the operation of the data signal line driving circuit sd.
On the other hand, there has been a strong demand for a liquid crystal display device of low electric power consumption recent years. Here, electric power consumption P is calculated by using the following equation (1):P=cfV2  (1)where an internal capacitance is c, a driving frequency is f, and the power supply voltage is V.
It has been attempted to keep the electric power consumption P low by lowering the driving frequency f. However, the electric power consumption P is in proportion to a square of the power supply voltage V. Therefore, lowering the power supply voltage V contributes more to lowering the electric power consumption P. However, as described above, the use of the AC drive may require a sufficiently high power supply voltage for the data signal line driving circuit sd, in order to be able to deal with a case where a potential change in the data signal lines due to the change in the potential Vcom of the counter electrode. It is a problem that this results in high electric power consumption.